On Chip Bus Tracer Based On Reverse Encoding In Soc

System on chip (SoC) is the integration of different components in to a single chip targeting a specific application. Real-time observability of the internal chip signals is crucial to SoC debugging, the obvious choice would be to use chip pins to observe them. However, this method is difficult to implement in the presence of high frequency internal clocks and limitation of the chip pins. A solution to this problem is to embed a bus tracer in SoC to capture bus signal, and to store the trace in on-chip storage (trace memory). The size of bus trace increases rapidly as the numbers of transactions are more. In order to reduce the trace size, compression is necessary. These compression mechanisms include slice compression, differential compression and dictionary based compression. The compression algorithms use forward encoding method i.e. first data is recorded as uncompressed and all others are encoded. Trace memory is a circular buffer, so in case of wrapping around this may result in loss of data and affects the decompression flow. Therefore a new reverse encoding method is used that results in efficient circular buffer utilization. To capture the bus signals, an on-chip communication architecture based on WISHBONE bus, with four masters and four slaves is designed and the hardware tracer based on reverse encoding is integrated to this. This is coded using VHDL, simulated using ModelSim 6.4c and synthesized using Xilinx ISE tool.